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1.8 v, 6 lvds/12 cmos outputs low power clock fanout buffer data sheet adclk846 rev. c document feedback information furnished by analog devices is believed to be accurate an d reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of pat ents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or pa tent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2009C2017 analog devices, inc. all rights reserved. technical support www.analog.com features selectable lvds/cmos outputs up to 6 lvds (1.2 ghz) or 12 cmos (250 mhz) outputs <16 mw per channel (100 mhz operation) 54 fs integrated jitter (12 khz to 20 mhz) 100 fs additive broadband jitter 2.0 ns propagation delay (lvds) 135 ps output rise/fall (lvds) 65 ps output-to-output skew (lvds) sleep mode pin-programmable control 1.8 v power supply applications low jitter clock distribution clock and data signal restoration level translation wireless communications wired communications medical and industrial imaging ate and high performance instrumentation functional block diagram out0 (out0a) out0 (out0b) out1 (out1a) out1 (out1b) out2 (out2a) out2 (out2b) out3 (out3a) out3 (out3b) out4 (out4a) out4 (out4b) out5 (out5a) out5 (out5b) lvds/cmos lvds/cmos clk ctrl_a ctrl_b sleep v ref clk adclk846 0 7226-001 figure 1. general description the adclk846 is a 1.2 ghz/250 mhz, lvds/cmos, fanout buffer optimized for low jitter and low power operation. possible configurations range from 6 lvds to 12 cmos outputs, including combinations of lvds and cmos outputs. two control lines are used to determine whether fixed blocks of outputs are lvds or cmos outputs. the clock input accepts various types of single-ended and differential logic levels including lvpecl, lvds, hstl, cml, and cmos. table 8 provides interface options for each type of connection. the sleep pin enables a sleep mode to power down the device. this device is available in a 24-pin lfcsp package. it is specified for operation over the standard industrial temperature range of ?40c to +85c.
adclk846 data sheet rev. c | page 2 of 15 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 gene ral description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 ti ming characteristics ................................................................ 4 clock characteristics ................................................................... 5 logic and power characteristics ................................................ 5 absolute maximum ratings ............................................................ 6 determining junction temperature .......................................... 6 esd caution .................................................................................. 6 thermal performance .................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ..............................................8 functional description .................................................................. 11 clock inputs ................................................................................ 11 ac - coupled applications ......................................................... 11 cloc k outputs ............................................................................. 12 control and function pins ........................................................ 12 power supply ............................................................................... 12 applications information .............................................................. 13 usin g the adclk846 outputs for adc clock applications ................................................................................ 13 lvds clock distribution .......................................................... 13 cmos clock distribution ........................................................ 13 inpu t termination options ....................................................... 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 revision history 9/2017? rev. b to rev. c changes to figure 2 .......................................................................... 7 updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 15 5/2010? rev . a to rev. b changes to integrated random jitter conditions ........................ 4 6/2009? rev . 0 to rev. a n o content updates ...................................................... throughout 4/2009? rev ision 0: initial version
data sheet adclk846 rev. c | page 3 of 15 specifications electrical character istics typical values are given for v s = 1.8 v and t a = 25c , u nless otherwise no ted. minimum and maximum values are given over the full v s = 1.8 v 5% and t a = ?40c to + 85c variation s, unless otherwise noted . input slew rate > 1 v/ns , unless otherwise noted. table 1 . parameter symbol min typ max unit conditions clock inputs differential input input frequency 0 1200 mhz input sensitivity, differential 150 mv p -p jitter performance is improved with higher slew rates (greater voltage swing) input level 1.8 v p -p larger voltage swings can turn on the protection diodes and can degrade jitter performance input c ommon - mode voltage v cm v s /2 ? 0.1 v s /2 + 0.05 v inputs are self - biased; enables ac coupling input common - mode range v cmr 0.4 v s ? 0.4 v inputs are dc - coupled with 200 mv p - p signal applied input voltage offset 30 mv inp ut sensitivity, single - ended 150 mv p -p clk ac - coupled; clk ac - bypassed to ground input resistance (differential) 7 k? input capacitance c in 2 pf input bias current (each pin) ?350 +350 a full input swing lvds clock outputs termination = 100 ?; differential (outx, outx ) output frequency 1200 mhz see figure 9 for a swing vs. frequency plot differential output voltage v od 247 344 454 mv v od 50 mv offset voltage v os 1.125 1.25 1.375 v v os 50 mv short - circuit current i s a, i s b 3 6 ma each pin (output shorted to gnd ) cmos clock outputs single - ended; termination = open outx and outx in phase output frequency 250 mhz with 10 pf load each output; see figure 16 for swing vs. frequency output voltage high v oh v s ? 0.1 v at 1 ma load v s ? 0.35 v at 10 ma load output voltage low v ol 0.1 v at 1 ma load 0.35 v at 10 ma load reference voltage v ref output voltage v s /2 ? 0.1 v s /2 v s /2 + 0.1 v 500 a output resistance 60 ? output current 500 a
adclk846 data sheet rev. c | page 4 of 15 timing characteristi cs table 2 . parameter symbol min typ max unit conditions lvds outputs termination = 100 ? differential; 3.5 ma output rise /fall time t r , t f 135 235 ps 20% to 80% measured differentially propagation delay, clk - to - lvds output t pd 1.5 2.0 2.7 ns v icm = v ref , v id = 0.5 v temperature coefficient 2.0 ps/c output skew 1 all lvds outputs on the same part 65 ps all lvds outputs across multiple parts 390 ps additive time jitter integrated random jitter 54 fs rms bw = 12 khz to 20 mhz , clk = 1000 mhz 74 fs rms bw = 50 khz to 80 mhz, clk = 1000 mhz 86 fs rms bw = 10 hz to 10 0 mhz, clk = 1000 mhz broad band random jitter 2 150 fs rms input slew rate = 1 v/ns crosstalk - induced jitter 260 fs rms calculate d from spur energy with an interferer 10 mhz offset from carrier cmos outputs termination = open output rise/ fall time t r , t f 525 950 ps 20% to 80%; cmos load = 10 pf propagation delay, clk - to - cmos output t pd 2.5 3.2 4.2 ns 10 pf load temperature coefficient 2.2 ps/c output skew 2 all cmos outputs on the same part 175 ps all cmos outputs across multiple parts 640 ps additive time jitter i ntegrated random jitter 56 fs rms bw = 12 kh z to 20 mhz , clk = 200 mhz broad band random jitter 3 100 fs rms input slew = 2 v/ns; s ee figure 11 crosstalk - induced jitter 260 fs rms calculated from spur energy with an interferer 10 mhz offset from carrier lvds - to - cmos output skew 2 lvds output(s) and cmos output(s) on the same part 0.8 1.6 ns cmos load = 10 pf and lvds load = 100 ? 1 this is the difference between any two similar delay paths while operating a t the same voltage and temperature. 2 measured at rising e dge of clock signal. 3 calculated from snr of adc method.
data sheet adclk846 rev. c | page 5 of 15 clock characteristics table 3 . clock output phase noise parameter min typ max unit conditions clk- to - lvds absolute phase noise input slew rate > 1 v/ns 10 00 mhz ?90 dbc/hz at 10 hz offset ?108 dbc/hz at 100 hz offset ?117 dbc/hz at 1 khz offset ?126 dbc/hz at 10 khz offset ?134 dbc/hz at 100 khz offset ?141 dbc/hz at 1 mhz offset ?146 dbc/hz at 10 mhz offset clk- to - cmos absolute phase noise input slew rate > 1 v/ns 200 mhz ?100 dbc/hz at 10 hz offset ?117 dbc/hz at 100 hz offset ?128 dbc/hz at 1 khz offset ?138 dbc/hz at 10 khz offset ?147 dbc/hz at 100 khz offset ?153 dbc/hz at 1 mhz offset ?156 dbc/hz at 10 mhz offset logic and power characteristics table 4 . control pin characteristics parameter symbol min typ max unit conditions control pins ( ctrl_a, ctrl_b, sl eep) 1 logic 1 voltage v ih v s ? 0.4 v logic 0 voltage v il 0.4 v logic 1 current i ih 5 8 20 a logic 0 current i il ?5 +5 a capacitance 2 pf power supply voltage requirement v s 1.71 1.8 1.89 v v s = 1.8 v 5% lvds outputs, full operation lvds a t 100 mhz 55 70 ma all outputs enabled as lvds and loaded, r l = 100 ? lvds at 12 00 mhz 110 130 ma all outputs enabled as lvds and loaded, r l = 100 ? cmos outputs, full operation cmos at 100 mhz 75 95 ma all outputs enabled as cmos and loaded, c mos load = 10 pf cmos at 250 mhz 155 190 ma all outputs enabled as cmos and loaded, c mos load = 10 pf sleep 3 ma sleep pin pulled high ; d oes not include power dissipated in external resistors power supply rejection 2 lvds psr tpd 0.9 ps/ mv cmos psr tpd 1.2 ps/ mv 1 these pins each have a 200 k? internal pull - down resistor. 2 change in t pd per change in v s .
adclk846 data sheet rev. c | page 6 of 15 absolute maximum rat ings table 5. parameter rating supply voltage v s to gnd 2 v inputs clk and clk ?0.3 v to +2 v cmos inputs ?0.3 v to +2 v outputs maximum voltage ?0.3 v to +2 v voltage reference voltage (v ref ) ?0.3 v to +2 v operati ng temperature range ambient ?40c to +85c junction 150c storage temperature range ?65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation b eyond the maximum operating conditions for extended periods may affect product reliability. determining junction t emperature to determine the junction te mperature on the application pcb , use the following formula : t j = t case + ( jt pd ) w here: t j is the j unction temperature ( c). t case is the c ase temperature ( c) measured by the customer at top center of the package . jt is indicated in table 6. pd is the p ower dissipation. va lu e s of ja are provided for package comparison and pcb design considerations. ja can be used for a first - order approximation of t j by the equation t j = t a + ( ja pd ) w here t a is the a mbient temperature ( c). values of jb are provided for package comparison and pcb design considerations. esd caution thermal performance table 6 . parameter symbol description value 1 unit junction - to - ambient thermal resistance ja still air per jedec jesd51 -2 0.0 m/sec airf low 57.0 c/w moving air jma per jedec jesd51 -6 1.0 m/sec air f low 49.8 c/w 2.5 m/sec air f low 44.7 c/w junction - to - board thermal resistance jb moving air per jedec jesd51 -8 1.0 m/sec airf low 35.2 c/w junction - to - case thermal resistance jc moving air per mil - std 883, method 1012.1 die - to - heat s ink 2.0 c/w junction - to - top - of - package characterization parameter jt still air per jedec jesd51 -2 0 m/sec airf low 1.0 c/w 1 results are from simulations. the pcb is a jedec multilayer type. thermal performance for actual applications requires carefu l inspection of the conditions in the application to determine if they are similar to those assumed in these calculat ions.
data sheet adclk846 rev. c | page 7 of 15 pin configuration and fu nction descriptions v ref clk clk v s ctrl_a ctrl_b out3 (out3a) v s out2 (out2b) out2 (out2a) out3 (out3b) v s sleep o ut5 (out5b) out5 (out5 a) out4 (out4b) out 4 (out4a) v s out1 (out1a) v s out0 (ou t0b) out0 (out0a) out1 (out1b) v s notes: 1. exposed paddle must be connected to gnd. 07226-002 2 1 3 4 5 6 18 17 16 15 14 13 8 9 10 11 7 12 20 19 21 22 23 24 adclk846 top view (not to scale) figure 2. pin configuration table 7. pin function descriptions pin no. mnemonic description 1 v ref reference voltage. 2 clk clock input (negative). 3 clk clock input (positive). 4, 10, 13, 16, 19, 22 v s supply voltage. 5 ctrl_a cmos input control for output 1 to output 0. (0: lvds, 1: cmos.) 6 ctrl_b cmos input control for output 5 to output 2. (0: lvds, 1: cmos.) 7 sleep cmos input for sleep mode. (0: normal operation, 1: sleep.) 8 out5 (out5b) complementary side of differential lvds output 5, or cmos output 5 on channel b. 9 out5 (out5a) true side of differential lvds output 5, or cmos output 5 on channel a. 11 out4 (out4b) complementary side of differential lvds output 4, or cmos output 4 on channel b. 12 out4 (out4a) true side of differential lv ds output 4, or cmos output 4 on channel a. 14 out3 (out3b) complementary side of differential lvds output 3, or cmos output 3 on channel b. 15 out3 (out3a) true side of differential lv ds output 3, or cmos output 3 on channel a. 17 out2 (out2b) complementary side of differential lvds output 2, or cmos output 2 on channel b. 18 out2 (out2a) true side of differential lv ds output 2, or cmos output 2 on channel a. 20 out1 (out1b) complementary side of differential lvds output 1, or cmos output 1 on channel b. 21 out1 (out1a) true side of differential lv ds output 1, or cmos output 1 on channel a. 23 out0 (out0b) complementary side of differential lvds output 0, or cmos output 0 on channel b. 24 out0 (out0a) true side of differential lv ds output 0, or cmos output 0 on channel a. (25) epad exposed paddle. the exposed paddle must be connected to ground.
adclk846 data sheet rev. c | page 8 of 15 typical performance characteristics v s = 1.8 v, t a = 25c, unless otherwise noted. ch2 100mv m 200ps 10.0gs/s ch1 C36.0mv 2 0 7226-003 figure 3. lvds output waveform at 1200 mhz 2.3 2.2 2.1 2.0 1.9 1.8 1.7 0.1 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 propatation delay (ns) input differential (v p-p) 07226-004 figure 4. lvds propagation delay vs. v id 5545 46 47 48 49 50 51 52 53 54 0 200 400 600 800 1000 1200 duty cycle (%) frequency (mhz) 07226-105 figure 5. lvds output duty cycle vs. frequency ch2 100mv m 1.0ns 10.0gs/s ch1 C36.0mv 2 0 7226-006 figure 6. lvds output waveform at 200 mhz 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 200 1600 1400 1200 1000 800 600 400 propagation delay (ns) input common-mode (mv) 07226-007 figure 7. lvds propagation delay vs. v cm 715675 685 695 705 1.62 1.92 1.82 1.72 differential output swing (mv p-p) power supply (v) 07226-014 figure 8. lvds output swin g vs. power supply voltage
data sheet adclk846 rev. c | page 9 of 15 900400 500 600 700 800 100200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 differential output swing (mv p-p) input frequency (mhz) 07226-009 figure 9. lvds differential output swing vs. input frequency 150 125 100 7550 25 0 0 200 400 600 800 1000 1200 1400 1600 1800 current (ma) frequency (mhz) 07226-110 figure 10. lvds current vs. frequency, all banks set to lvds 500450 400 350 300 250 200 150 100 50 0 02 . 5 2.0 1.5 1.0 0.5 jitter (f s rms) input slew rate (v/ns) 07226-011 figure 11. additive broadband jitter vs. input slew rate C 80 C90 C100C110 C120 C130 C140 C150 C160 C170 C180 10 100m 10m 1m 100k 10k 1k 100 phase noise (dbc/hz) frequency offset (hz) absolute phase noise measured @ 1ghz with agilent e5052 using wenzel clock source consisting of a wenzel 100mhz crystal oscillator (p/n 500-06672), wenzel 5 multiplier (p/n lnom-100-5-13-14-f-a), and a wenzel 2 multiplier (p/n lndd-500-14-14-1-d). 07226-112 clock source adclk846 figure 12. absolute phase noise lvds at 1000 mhz 200 0 50 100 150 25 50 75 100 125 150 175 225 200 250 current (ma) frequency (mhz) 07226-113 both banks cmos bank a cmos, bank b lvds bank a lvds, bank b cmos both banks lvds figure 13. lvds/cmos current vs. frequency with various logic combinations 5545 46 47 48 49 50 51 52 53 54 0 50 100 150 200 250 duty cycle (%) frequency (mhz) 07226-114 figure 14. cmos output duty cy cle vs. frequency, 10 pf load
adclk846 data sheet rev. c | page 10 of 15 ch1 300mv 1.25ns/div ch1 954mv 1 0 7226-115 figure 15. cmos output waveform at 200 mhz, 10 pf load 07226-116 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 50 100 150 200 250 output swing (v) frequency (mhz) 25c 85c figure 16. cmos output swing vs. fr equency and temperature, 10 pf load 07226-017 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0 50 100 150 200 250 c l = 5pf c l = 10pf c l = 20pf output swing (v) frequency (mhz) figure 17. cmos output swing vs. frequency and capacitive load ch1 300mv 5.0ns/div ch1 954mv 1 0 7226-018 figure 18. cmos output waveform at 50 mhz, 10 pf load 1.8 1.4 1.5 1.6 1.7 02 5 0 200 150 100 50 output swing (v) frequency (mhz) r l = 1k ? r l = 750 ? r l = 500 ? r l = 300 ? 07226-015 figure 19. cmos output swing vs . frequency and resistive load
data sheet adclk846 rev. c | page 11 of 15 functional descripti on th e adclk846 clock input is distributed to all output cha nnels. each channel bank is pin programmable for either lvds or cmos levels. this allows the selection of multiple log ic configurations ranging from 6 lvds to 12 cmos outputs, along with other combinatio ns using both types of logic. c lock inputs the differential inputs of the adclk846 are internally self - biased. the clock inputs have a resistor divider , which sets the common - mode level for the inputs. the complementary inputs are biased about 30 mv lower than the true input to avoid oscil lations if the input signal ceases . see figure 20 for the equivalent input circuit. the inputs can be ac - coupled or dc -coupled. table 8 displays a guide for input logic compatibility. if a si ngle - ended input is desired , this can be accommodated by ac or dc coupling to one sid e of the different ial input. bypass t he other input to ground by a capacitor. note that j itter performance degrades with low input slew rate, as shown in figure 11 . see figure 28 through figure 32 for different termination schemes. 9k? 9.5k? 9k? 8.5k? v s clk clk gnd 07226-023 figure 20 . adclk846 input stage ac-co upled applications when ac coupling is desired, th e adclk846 offers two options. the first option requires no external components (excluding the dc blocking cap acitor ); it allows the user to couple the reference signal onto the clock input pins (s ee figure 31 ). the second op tion allows the use of the v ref pin to set the dc bias l evel for the adclk846. the v ref pin can be connected to clk and clk through resistors. this method allows lower impedance terminati on of signal s at the adclk846 (s ee figure 32 ). t he internal bias resistors are still in parallel with the external biasing. however, the relatively high impedance of the internal resistors allows the external termination to v ref to dominate. this is also useful if it is not desirable to offset the inputs sligh tly as previously mentioned using only the internal biasing. table 8. input logic compatibility supply (v) logic common mode (v) output swing (v) ac - coupled dc - coupled 3.3 cml 2.9 0.8 yes not allowed 2.5 cml 2.1 0.8 yes not allowed 1.8 cml 1.4 0.8 yes yes 3.3 cmos 1.65 3.3 n ot allowed not allowed 2.5 cmos 1.25 2.5 not allowed not allowed 1.8 cmos 0.9 1.8 yes yes 1.5 hstl 0.75 0.75 yes yes lvds 1.25 0.4 yes yes 3.3 lvpecl 2.0 0.8 yes not allowed 2.5 lvpecl 1.2 0.8 yes yes 1.8 lvpecl 0.5 0.8 yes yes
adclk846 data sheet rev. c | page 12 of 15 clock o utputs each driver consists of a differential lvds output or two single - ended cmos outputs (always in phase). when the lvds driver is enabled, the corresponding cmos driver is in tristate . w hen the cmos driver is enabled, the corresponding lvds driver i s powered down and trist ated. figure 21 and figure 22 display the equivalent output stage. outx outx 3.5ma v s 3.5ma 07226-024 figure 21 . lvds output simplified equivalent circuit outxa v s outxb v s 07226-025 figure 22 . cmos equivalent output circuit control and function pins logic select for ctrl_a ctrl_a s elects either cmos (high) or lvds (low) logic for output 1 and output 0. this pin has an internal 20 0 k pull - down resistor. logic select for ctrl_b ctrl_b s elects either cmos (high) or lvds (low) logic for output 5 , output 4, output 3, and output 2 . this pin has an internal 20 0 k pull - down resistor. sleep mode sleep powers down the chip except for the band gap. the input is active high, which puts the outputs into a high - z state. this pin has a 200 k pull - down resistor. t he control pins are operational during sleep mode . p ower supply the adclk846 requires a 1.8 v 5% power supply for v s . best practice recommends bypassing the power supply on the pcb wit h adequate capacitance ( >10 f) and bypassing all power pins with adequate capacitance (0.1 f) as close to the part as possible. the layout of the adclk846 evaluation board (adclk846/pcb z ) provides a good layout example. exposed metal paddle the exposed metal paddle on the adclk846 package is an electrical connection, as well as a thermal enhancement. for the device to function properly, the paddle must be properly attached to ground (gnd). the adclk846 dissipate s heat through its exposed paddle. the pcb acts as a heat sink for the adclk846 . the pcb attachment must provide a good thermal path to a larger heat dissipation area, such as the ground plane on the pcb. this requires a grid of vias from the top layer down to the ground pl ane. see figure 23 for an example. vias to gnd plane 07226-026 figure 23 . pcb land example for attaching exposed paddle
data sheet adclk846 rev. c | page 13 of 15 applications information using the adclk846 outputs for adc clock applications any high speed analog - to - digital converter (adc) is extremely sensitive to the quality of the sampling clock provided by the user. an adc can be thought of as a sampling mixer , and any noise, distortion, or timing jitter on the clock is combined w ith the desired signal at the a dc output. cl ock integrity require - ments scale with the analog input frequency and resolution, with higher analog input frequency applications at 14 - bit resolution being the most stringent. the theoretical snr of an adc is limited by the adc resolution and the jitter on the sampling clock. considering an ideal adc of infinite resolution where the step size and quantization error can be ignored, the available snr can be expressed approximately by ? ?? ? ? ?? ? = j a tf snr 2 1 20log w here : f a is the highest analog frequency being digitized. t j is the rms jitter on the sampling clock. figure 24 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (enob). see an - 756 application note and an - 501 application note for more informatio n. f a full-scale sine wave analog frequency (mhz) snr (db) enob 10 1k 100 30 40 50 60 70 80 90 100 110 6 8 10 12 14 16 18 t j = 100 f s 200 f s 400 f s 1ps 2ps 10ps snr = 20log 1 2 f a t j 07226-027 figure 24 . snr and enob vs. analog input frequency many high performance adcs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy pcb. distributing a single - ended clock on a noisy pcb can result in coupled noise on the sample clock. differential distribution has inherent common - mode rejection that can provide superior clock perf ormance in a noisy environment. the adclk846 features lvds outputs that provide differential clock outputs, which enable clock solutions that maxim ize con - verter snr performance. consider the input requirements of the adc (differential or single - ended, logic level, termination) when selecting the be st clocking/converter solution. lvds clock d istribution the adclk846 provides clock outputs that are selectable as either cmos or lvds level outputs. lvds is a differential ou tput option that uses a current - mode output stage. the nominal current is 3.5 ma , which yields 350 mv output swing across a 100 ? resistor. the lvds output meets or exceeds all ansi/tia/eia - 644 specifications. a recommended termina - tion circuit for the lvds outputs is shown in figure 25 . if ac coupling is necessary, place decoupling capacitors either before or after the 100 ? termination resistor. v s lvds 100? differential (coupled) v s lvds 100? 07226-028 figure 25 . lvds output termination see the an - 586 application note at www.analog.com for more information on lvds. cmos c lo ck d istribution the output drivers of the adclk846 can also be configured as cmos drivers. when selected as a cmos driver, each output becomes a pair of cmos outputs . these outputs are 1.8 v cmos compatible. when single - ended cmos clo cking is used, some of the following guidelines outlined in this section apply . design p oint - to - point connections such that each driver has only one receiver, if possible. connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. the value of the resistor is depe ndent on the board design and timing requirements (typically 10 ? to 100 ? is used). cmos outputs are also limited in terms of the capacitive load or trace length that they can drive. typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity. cmos cmos 10? 60.4? (1.0 inch) microstrip 07226-076 figure 26 . series termination of cmos output
adclk846 data sheet rev. c | page 14 of 15 termination at the far end of the pcb trace is a second option. the cmos outputs of the adclk846 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in figure 27. match the far-end termination network to the pcb trace impedance and provide the desired switching point. the reduced signal swing may still meet receiver input requirements in some applications. this can be useful when driving long trace lengths on less critical nets. cmos cmos 10 ? 50 ? 100 ? 100 ? v s 0 7226-077 figure 27. cmos output wi th far-end termination because of the limitations of single-ended cmos clocking, consider using differential outputs when driving high speed signals over long traces. the adclk846 offers lvds outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters. input termination options for single-ended operation, always bypass unused input to gnd as shown in figure 31. figure 32 illustrates the use of the v ref to provide low imped- ance termination into v s /2. in addition, figure 32 shows a way to negate the 30 mv input offset with external resistor values. for example, use 1.8 v cmos with long traces to provide far- end termination. 100 ? clk clk 100 ? clk clk 0 7226-128 figure 28. typical ac-coupled or dc-c oupled lvds or hstl configurations (see table 8) clk clk clk clk v cc v cc 0 7226-129 figure 29. typical ac-coupled or dc-coupled cml configurations (see table 8 for cml coupling limitations) clk clk 50 ? 50 ? v cc C 2v clk clk 50 ? 50 ? v cc C 2v 07226-130 figure 30. typical ac-coupled or dc -coupled lvpecl configurations (see table 8 for lvpecl dc coupling limitations) clk clk clk clk clk clk 07226-131 figure 31. typical 1.8 v cmos configurations for short trace lengths (see table 8 for cmos compatibility) clk clk v ref 07226-132 figure 32. use of the v ref to provide low impedance termination into v s /2
data sheet adclk846 rev. c | page 15 of 15 outline dimensions 0.80 0.75 0.70 pkg-003994/5111 0.50 bsc 0.50 0.40 0.30 compliant to jedec standards mo-220-wggd-8 bottom view top view 4.10 4.00 sq 3.90 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 pin 1 indicator 1 24 7 12 13 18 19 6 03-09-2017-b 0.30 0.25 0.20 0.20 min 2.44 2.30 sq 2.16 exposed pad seating plane p i n 1 i n d i c a t o r a r e a o p t i o n s ( s e e d e t a i l a ) detail a (jedec 95) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 33. 24-lead lead frame chip scale package [lfcsp] 4 mm 4 mm body and 0.75 mm package height cp-24-14 dimensions shown in millimeters ordering guide model 1 temperature range package description package option adclk846bcpz ?40c to +85c 24-lead lfcsp cp-24-14 adclk846bcpz-reel7 ?40c to +85c 24-lead lfcsp cp-24-14 adclk846/pcbz evaluation board 1 z = rohs compliant part. ?2009C2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07226-0-9/17(c)

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